What is ASIC?
An application-specific integrated circuits (ASIC), one kind of semiconductors, is an integrated circuit (IC) customized for a particular use, generally with some combined functions, rather than intended for general-purpose use. The so-called “ASIC” is made of digital circuits and composed of various kinds of semiconductors except a single function IC and high performance calculation ICs. By the late 1990s, some manufacturers launched such ASICs with certain SRAM (Static Random Access Memory) functions, while others produced such ASICs with Flash Memory.
- Smaller size of mounting space is realized
- Power consumption is low
- Operational Speed has improved
- Low Unit Cost
- Higher development cost
- Longer Turnaround Time for Development
- Circuit Design modifications and change or re-fabrication of metal are difficult
Gate Array design is a manufacturing method in which the diffused layers, i.e., transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization or set “unconnected”. Non-recurring engineering costs become much lower as photolithographic masks are required only for the metal layers, and production cycles are much shorter, as metallization is a relatively quick process. On the other hand, density and performance would get worse because Gate Array contains a mix of standard gates.
Every ASIC manufacturer can produce various functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, that could also be represented in third-party tools. Standard-cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard-cell design fits between Gate Array and Full Custom design in terms of both its non-recurring engineering and recurring component cost.
The embedded array uses the cell-based IC libraries of high-performance function blocks with combination of the existing Gate Arrays; i.e., a mix of Cell bases and Gate Arrays.
Structured ASIC is an intermediate technology between ASIC and FPGA. In a “structured ASIC” design, the logic mask-layers of a device are predefined by the ASIC vendor or in some cases by a third party and by incorporating SRAM, PLL for clock, I/O interface and/or other general use units available in the market, you can expect shorter manufacturing cycle time and design cycle time as well. Only a small number of chip layers must be custom-produced. The structured ASIC needs much less non-recurring engineering expenses (NRE) than “standard-cell” or “”full-custom” chips, which require that a full mask set be produced for every design.
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